EDN

Rambus Introduces Memory Controller Interface Solution for Industry-standard DDR3 DRAM

Rambus Inc. has announced the introduction of its memory controller interface solution for industry-standard DDR3 DRAM. The fully integrated hard macro cell provides the physical layer (PHY) interface ...
EDN

ARM Introduces LPDDR2 Memory Controller to Accelerate Chip Performance and Improve Energy Saving

CAMBRIDGE, UK – Oct. 7, 2008 – ARM [(LSE: ARM); (Nasdaq: ARMH)] today announced the ARM PrimeCell low-power DDR2 (LPDDR2) dynamic memory controller (PL342), which provides a high-performance interface ...
TweakTown

SK hynix unveils DRAM memory chip roadmap for the next 30 years: 4F2VG tech, 3D DRAM, and more

TL;DR: SK hynix unveiled a 30-year DRAM roadmap featuring 4F2 Vertical Gate and 3D DRAM technologies to enhance performance, integration, and power efficiency beyond 10nm scales. These innovations aim ...
Semiconductor Engineering

Smaller Geometries, Bigger Demands: The Role Of OCD In GAA Logic And Vertical Gate DRAM Process Control

AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, ...
Embedded

High-bandwidth memory (HBM) options for demanding compute

Explosive growth of generative artificial intelligence (AI) applications in recent quarters has spurred demand for AI servers and skyrocketing demand for AI processors. Most of these processors — ...